RedHawk-EV is the next generation dynamic power analysis and verification solution which combines Apache's silicon-proven full-chip Vectorless Dynamic physical power integrity with the new EV technology for power closure sign-off.

RedHawk, with integrated transistor-level characterization, accurately analyzes the effects of on-chip and off-chip (package) inductance, simultaneous switching (core, memory, I/O) noise, and decoupling capacitance (intentional and intrinsic), as well as the impact of dynamic voltage drop on timing for high performance SoCs.

The addition of EV technology enables the designers to explore and identify physical design weaknesses and automatically repair the source of supply noise. The new database technique within the EV technology delivers unsurpassed capacity to meet the challenges of today and future designs. By using RedHawk, designers can reduce the likelihood of a chip re-spin while improving yield.

RedHawk Benefits

Capability Highlights

Power Closure Sign-off Requirements

Transistor-level Accuracy with Cell-Based Capacity and Speed

Vectorless Dynamic and Extended Power Space Coverage

Automatice Noise Repair by Grid Fixing and Decap Placement

RedHawk Power Closure Flow

RedHawk Benefits

• Certified in TSMC Reference Flow 5.0 and 6.0 for power closure flow
• SoC capacity with transistor-level accuracy
• Full-chip coverage with Vectorless Dynamic
• Identify dynamic "hot spots" and its impact on timing
• Accurately pinpoint the location of physical design weaknesses
• Automatically repair the source of noise
• Obtain robust and reliable decoupling capacitance protection
• Eliminate excessive decoupling capacitance for leakage control
• Proven accuracy through correlation with SPICE and measured silicon
• Reduce wasted resources from over-designed grids
• Increase yield and lower the risk of silicon failures

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Capability Highlights

• Static IR-drop, EM, and dynamic voltage drop (DvD)
• Integrated transistor-level cell, memory, and I/O characterization
• Full-chip RLC network extraction, including self and mutual inductance
• Vectorless Dynamic with power, network, and timing awareness
• Dynamic impact on timing analysis
• Physical design weaknesses exploration and identification
• Wire fixing and optimization, including non-uniform grids
• Decoupling capacitance advisory and optimization
• Clock-tree analysis, "What-If" analysis
• Native support for GDSII memories and 45 degree geometries
• Advanced low power and leakage control designs
• Global I/O SSO and ground-bounce verification
• High capacity embedded SPICE simulation

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Power Closure Sign-off Requirements

As designs move towards 90nm and below processes, power supply noise and its related issues are becoming a critical concern. More and more designs are experiencing timing slow down and functional failures due to the power grid noise. To address these issues, leading foundry sign-off flows have added power closure requirements.

Power supply noise consists of resistive network drop (or IR drop) and inductive element induced noise (di/dt), and therefore requires a highly accurate full-chip transient simulation solution that provides a complete picture of the dynamic voltage profile in the design. RedHawk provides silicon-proven Vectorless Dynamic simulation approach that considers resistive, inductive, and capacitive elements from the chip package and on-die grid, the dynamic current drawn by simultaneously switching outputs, and the capacitive loads present in the design.

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Transistor-level Accuracy with Cell-Based Capacity and Speed
RedHawk performs true full-chip transient simulation considering all power-ground RLC parasitics, as well as the SPICE current waveforms for each cell from the Apache Power Libraries, yielding accurate voltage drop waveforms at each cell instance. The instance-based dynamic waveforms facilitate accurate analysis of the dynamic impact to chips' timing, and the ability to determine the precise amount and location of decoupling capacitance as well as wire fixing that are needed. Typically, the transient simulation voltage waveforms are within 2% of SPICE and measured silicon.

Additionally, memory content of SoCs continue to grow, consuming already well over half of the total available real estate today. Due to their custom design style, these memories are typically represented in a GDSII format. RedHawk extracts GDSII memories with the correct current profile for inside of the memory, thus providing much more accurate view of the full-chip dynamic voltage drop and silicon behavior.

RedHawk's EV technology supports a new database technique that essentially eliminates the design capacity limitation. With EV, designers can trade-off the run-time performance with the physical memory size of their machine. Based on the available memory space, RedHawk automatically loads the database from cache, as needed, for high-capacity high-performance analysis and verification.

The new EV technology natively supports 45-degree geometries, such as those commonly found in flip-chip designs. Instead of fracturing the polygon into multpiple layers, EV's native support of such structures significantly reduces the design database requirements, thus resulting in higher capacity verification.

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Vectorless Dynamic and Extended Power Space Coverage
RedHawk provides extended power space exploration to broaden the coverage and accurately pinpoint the location of phsyical design weaknesses. RedHawk's innovative Vectorless Dynamic technology, with correlation results within 5% of SPICE, computes the statistical worst-case switching scenarios and event sequences for peak dynamic voltage drop without requiring a VCD file or user-provided vectors. In determining the cause of the dynamic "hot-spots", RedHawk's EV technology considers

• Power-based constraints within a STA driven timing window
• Power/ground network structural weaknesses
• Timing conditions such as slack and critical paths

By accurately pinpointing the location of physical design weaknesses and determing their impact on dynamic voltage drop and ground bounce, desingers can not only verify potential power-related functional and timing behavior, but can also avoid excessive over-design.

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Automatic Noise Repair by Grid Fixing and Decap Placement
Once the dynamic "hot spots" are identified and their cause determined, RedHawk automatically repairs the source of noise by either fixing the grid or placing decap protections or both. Traditionally, the designers over-design the grid and fill all the empty cells with decoupling capacitance (decap) to reduce the risk of power supply noise related issues close to tapeout. But at 90nm and below processes, designers can no longer afford to guard band their designs. Also, decaps placed too far from the source of the noise does little in reducing the dynamic noise. Worse yet, ineffective decaps can increase the total leakage current in the design, creating additional power integrity issues.

RedHawk with its' EV and optional Fix and Optimize (FAO) technology provides accurate grid optimization and repair capability at full-chip and at the regional-level. Without compromising the total voltage drop, RedHawk increases metal resources to the areas of dynamic "hot spots", while reducing the metal widths of the areas with low voltage drop to avoid over-designing. RedHawk's non-uniform grid optimization allows designers to specify constraints such as area, metal layers, and target drop to be considered for optimization. Since the optimization engine is tightly integrated with RedHawk's proven dynamic analysis engine, the designers can feel confident with the accuracy of the optimized grid.

Along with grid optimization, RedHawk's EV and FAO technology provides decap placement advisory for reducing dynamic voltage drop. Since decaps serve as local reservoirs of charge, their placement should be targeted such that they effectively reduce power and ground noise without adding unnecessary leakage current. RedHawk intelligently places decaps by considering the simultaneous switching effects, as well as removes unnecessary decaps which contribute to overall leakage current. RedHawk offers both decap advisory and repair where in the advisory mode, it provides feedback to the designers on where decaps should be placed, and whereas in the repair mode, it places decaps in legalized placement areas to reduce the dynamic "hot spots". RedHawk's decap advisory and placement capability is based on it's accurate dynamic power analysis engine with feedback to timing analysis.

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RedHawk Power Closure Flow

RedHawk delivers complete power closure flow from prototyping to sign-off. Not only does RedHawk identify the location of dynamic "hot spots", it determines the cause of the problem by accurately pinpointing the power/ground network weaknesses, and automatically repairs the sources of noise. RedHawk takes power integrity analysis and verification to the next level by offering solutions that will enable designers to quickly reach power closure.

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Resources:

Correlation Results - CICC 2004

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