NSPICE is the industry's first mixed-domain simulator with support for actual S-parameter data, without translation or fitting. The product provides a seamless and accurate simulation path - from chip to package to board to backplane and back to chip - using direct S-parameters, thereby eliminating the inaccuracies of lumped RLC model approximations.

In addition, NSPICE provides dramatic performance and capacity improvements over existing SPICE and easily drops into all simulation environments with full compatibility to HSPICE netlists and commands. NSPICE is targeted for system integrators and designers of chips, boards, connectors, and backplanes for the high-speed, multi-gigabit communications, networking, and graphics markets.

NSPICE-PI, targeted at I/O SSO verification, enables true-SPICE accurate simulation of hundreds of I/O buffers together with the extracted power-ground network. NSPICE-PI adds BLSN (Big Linear, Small Non-linear) solver, on top of the C++ modern data structure NSPICE engine.

NSPICE-UBS directly reads in accurate S-parameter data and calculates the precise time step (in picoseconds) to replicate the high-frequency signal, while running fast enough to cover the long simulation span.

Highlights

Performance

Multi-Gigabit SERDES System Simulation

Highlights

• True SPICE accuracy, proven by silicon measurements
• 20x+ capacity and 10x+ performance over SPICE simulation
• Mixed-domain simulation with direct support for S-parameter enabling simulation between chip, package, board, and backplane
• BLSN (Big Linear, Small Non-linear) solver supports concurrent simulation of Vdd/Vss network, I/O transistors, and frequency based package models required for I/O SSSO verification
• Works across a broad range frequency range, up to 20+ GHz
• Complete HSPICE compatibility

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Performance

Circuit Type	Number of Mosfets	Number of Rs/Cs/Ls	NSPICE CPU	Traditional SPICE CPU	NPSICE Memory	Traditional SPICE Memory
0.12 um flip-flop	40	148 Rs / 340 Cs	0.5 sec.	91.35 sec.	5.6 MB	3 8MB
PLL	614	7 Rs / 22 Cs	887 min.	1656 min.	1.5 MB	3.5 MB
A/D converter	3009	129 Rs / 79 Cs	400 min.	400 min.	12 MB	52 MB
DRAM	23,800	742 Rs / 2204 Cs	42 min.	174 min.	72 MB	249 MB
Serdes driver	42,208	1161 Rs/ 1091 Cs/ 1040 Ls	40 hrs.	Failed	86.9 MB	Failed
SRAM	250,000	354 Rs	3.5 hrs.	Failed	510 MB	Failed

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Multi-Gigabit SERDES System Simulation

Following diagram shows SERDES simulation system (>10K transistors & >100K RCs) with S-parameters.

• SPICE model for Tx and Rx
• S-parameter models for backplane, connector, and line cards
• Transmission line model for cables

NSPICE takes in direct S-parameters for backplanes, connectors and line cards.

Following waveform shows direct S-parameter simulation of a multi-gigabit transceivers combined with multiple PLLs. NSPICE results accurately match the measured data.

Following shows the eye-diagram generated by NSPICE.

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Resources:

Article:NSPICE Bridges Simulation Gap

FAQ

Product Evaluation

NSPICE Encrytion Request

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