Advanced Low Power Design
Low power design has become synonymous with mobile telecommunications and portable computing system designs. The advancements in silicon process technology offer smaller transistors and higher packaging density but suffer from increased power consumption, especially for high-speed, high-data-rate systems.

In order to lower power consumption and control leakage currents, design techniques such as power-gating, Vdd-stepping, and substrate-biasing have been deployed. These techniques save power by turning off inactive blocks, lowering Vdd when the chip is inactive, or raising the back-biasing of inactive blocks to reduce leakage. But these techniques further complicate the analysis and verification of the physical power integrity.

One of the common issues with low power designs is that it may incur severe supply fluctuations or current spikes during state transition from active to inactive or vice versa. It is crucial to understand what the peak current surge will be when an inactive block is powered back on. Also, many devices contain data retention networks that save the state of the block once it is shut down. Analyzing the effect of these retention networks is very critical to the power integrity of the device. An accurate verification of these effects require a true transient (time-point-by-time-point) simulation at the full-chip level to consider the interaction between active, inactive, and transient blocks.

RedHawk is the only full-chip dynamic physical power integrity solution that delivers cell-level capacity and performance with transistor-level accuracy. It uses a proprietary power library (APL) tool to accurately characterize the dynamic power for each cell based on its current waveforms. It performs a true transient simulation while considering the effects of power gates and nonlinear capacitive loading, as well as package RLC and decoupling capacitance.

For accurate dynamic power analysis, RedHawk supports advanced low-power design techniques such as:

• Multiple Vdd domains
• Power-gate (header switch)
• Leakage-control back-biasing
• Transient power-on ramp-up

As designers tackle the challenges of low power design, there needs to be a power verification solution that can accurately provide the visibility of their physical power integrity prior to tape-out. Static IR-drop solution does not have any concept of time, which is critical in determining the power consumption as power switches on and off to various portions of the design. RedHawk provides full-chip transient simulation for power-on ramp-up analysis with the ability to handle multiple Vdd domains, header switches, and back-biasing designs.