Power Grid Prototyping, Optimization, and Fixing

Over-designed grid and ineffective decap placements
Timing and functional failures caused  by power grid noise are becoming a critical design issue for 90nm and 65nm processes.  For designs using advanced processes, it is no longer adequate to rely on the traditional method of over-designing the power supply network and populating all available spaces with decoupling capacitance (decap).  An over-designed power grid wastes resources and impacts routing and timing convergence. Ad-hoc decap placement is not only ineffective in suppressing power supply noise but also results in excessive leakage current.

Traditionally, power grid design has been based on heuristics or experience. Typically, the power networks are uniform in width and pitch across a design. Once designed, the power routes remain unchanged, unless the voltage drop verification performed prior to tape-out indicates problems.  Unfortunately, this approach does not allow designers to optimize the grid for a particular design based on its unique power consumption, and results in a grid that is uniformly over or under-designed.  Also, any problems found in the grid design are not addressed until late in the design cycle.

Also, an ad-hoc method of intentional decap placement does little for minimizing power grid noise, as these decaps are usually placed in empty cell rows where the switching activity is relatively low to be effective. Additionally, indiscriminate decap placement can adversely affect a design through increase in leakage current, which is a major concern given that about 30% of a chip’s total power in 90nm designs comes from leakage current.

Power-aware physical design methodology
What’s needed is a power aware physical design methodology that includes power supply planning, resource allocation, and design (package, decap, and power grid network) along with sign-off quality verification.  The new methodology helps designers achieve faster design closure and insure them against impact to schedule caused by late changes, chip failures, and production yield reduction.

Power-aware physical design methodology starts early in the design cycle, with a prototyping solution. The solution must deliver quick turnaround time so that the designers can generate multiple grids for various constraints, such as different floorplan or power consumption scenarios, and gain estimates on routing resource requirements.  Once the prototyped grid is selected, a grid optimization solution allows the designers to change the power routes for a most optimal design.

Later in the design stages when placement is more defined, a grid fixing solution provides targeted wire fixes to resolve voltage drop issues. In addition, an automated decap advisory solution will enable designers to place decaps in a targeted manner to control the dynamic hot-spots, while minimizing the impact of decap leakage current.

Apache’s power-aware physical design flow provides a prototyping solution for the initial power/ground (P/G) route definition, an optimization of the P/G grid along the design cycle, automatically fixes P/G grid issues late in the design cycle, advises on decap requirements, and places decaps in a targeted manner.

Apache’s SkyHawk provides power grid planning and prototyping solution and RedHawk-EV allows power grid optimization and fixing for both wires and decaps. SkyHawk and RedHawk-EV are based on RedHawk’s highly accurate full-chip transient simulation engine that provides design’s complete picture of the dynamic voltage profiles. It considers resistive, inductive, and capacitive elements from the chip package and on-die grid, the dynamic current drawn by simultaneously switching outputs, and the capacitive loads that are present in the design.

Power/Ground Grid Prototyping
SkyHawk allows designers to explore different power grid design options for various design scenarios. It is flexible enough to work in very early stages of the design, when minimal placement information is available or in slightly more defined phases, when early placement information is available and the scope for defining the global and/or local power grid exists.

SkyHawk is constraint driven to meet user-defined voltage drop targets while honoring specific routing resource usage restrictions. It generates multi-layer power grids that honor blockages and electromigration limits, explore pad placement options, generate rings if needed, etc.  SkyHawk offers the ability to explore non-uniform grid options where the grid size is increased in the high power regions, while reduced in non-critical regions to save resources.

SkyHawk results allow designers to observe the routing resource requirements for different power consumption and voltage drop scenarios early in the design process.  This enables the design teams to anticipate routing congestion issues earlier in the design cycle and use a power grid that can withstand changes in the power consumption during the design cycle.

Power/Ground Grid Optimization and Fixing
The P/G Fix and Optimization (FAO) engine within RedHawk-EV provides a fast and effective way to address on-die power supply issues, including global and targeted local fixes.  FAO uses RedHawk’s efficient power grid RLC extraction and accurate static and dynamic analysis engines to identify, isolate, fix, and verify voltage drop issues.

As a design evolves, the prototype grid created using SkyHawk should be optimized to reflect the design changes that take place throughout the design cycle. RedHawks’s FAO engine can globally redefine the grid based on user provided restrictions such as pitches and track requirements. With RedHawk, designers can first determine the voltage drop budget and then automatically optimize the grid to meet the voltage drop target while minimizing the grid’s metal routing usage.

Once the placement is performed and the routing and timing optimization is on-going, it is not possible to globally optimize the power grid. At this phase, RedHawk’s FAO engine performs non-uniform targeted fixes on the grid to address the voltage drop “hot-spots”.

Typically, a design’s power density is non-uniform, where “hot-spots” are often present in the areas with clock buffers. RedHawk’s FAO considers this and allocates more metal resources to the higher voltage drop areas compared to the sparse cell placement areas.  It widens the power grid only around the “hot-spot” area and shrinks it in other areas, without compromising the total voltage drop.

Decap Advisory and Placement
Decaps serve as local reservoirs of charge and when placed in a targeted manner, can reduce the power and ground noise to acceptable limits. However, if decaps are placed in an ad-hoc manner, they add unnecessary leakage current while being ineffective in reducing the dynamic voltage drop. Therefore, for decaps to be effective, they must be placed closer to the switching areas.

RedHawk-EV’s decap advisory and placement engine provides feedback to the designers about where decaps are needed and places decaps in legalized placement areas. In an advisory mode, the solution provides the locations of where the decap placement would be most effective. It suggests the total amount of decaps needed in the region with dynamic voltage drop violation and enables users to make the determination on whether to place the decaps or not.

In the placement (or fixing) mode, RedHawk redefines the placement location of decaps that will reduce the dynamic voltage drop while optimizing the decap induced leakage current. It identifies and removes decaps from locations that are ineffective in reducing dynamic voltage drop and only adds decaps where there’s enough room and where their presence will help reduce the dynamic voltage drop.

Often times, insertion of decaps alone does not reduce dynamic voltage drop completely, so RedHawk-EV gives users the ability to concurrently perform decap and wire fix and optimization to reach their desired voltage drop targets. Decap and/or wire fixing can be performed at the block or full-chip level.

Apache’s power-aware physical design methodology allows engineers to design a chips’ power supply that helps mitigate P/G noise induced design failures and avoid late design changes. SkyHawk enables fast and effective power grid prototyping, while RedHawk-EV, the next generation physical power integrity solution, integrates optimization, fixing and verification for faster and effective design closure.