Global I/O SSO
As process technology advances and design complexity increases, more chip failures due to I/O SSO problems are being reported industry-wide. I/O SSO refers to the signal distortion created by the supply noise caused by simultaneous switching of multiple outputs. With many simultaneous switching I/Os, the amount of current being drawn can be staggering. Ground bounce becomes a significant issue and can push signal delays out past the acceptable windows. This is especially critical for multi-gigabit I/Os, where ground bounce and a shared Vss can disturb digital logic in the I/Os or core cells near the I/O buffers.

While most power-supply analysis is focused on the on-chip supply distribution, I/O SSO effects are related to interaction between the on-chip supplies, driver circuits, package, and PCB board. The supply noise created by I/O SSO can lead to a number of issues such as:

• Delay pushed out due to supply noise at the output driver
• Data line signal distortion such as porches and glitches
• Increased timing jitter on signal lines
• Input signal glitches
• Impact to the core Vdd/Vss noises

Analysis of I/O SSO requires the simulation of package and on-chip circuitry in the same simulation deck. Therefore it must support the model format used for the package as well as on-chip circuitry.

Apache addresses the need for Global I/O SSO flow with the combination of its RedHawk and NSPICE products. This flow offers a global solution of integrated P/G network extraction, netlist generation, and true-spice simulation to analyze the chip-package-board interaction with true-spice accuracy on a large number of I/O buffer cells and large package models.

The RedHawk engine extracts industry standard data formats such as LEF/DEF/GDSII at the full-chip level, and accurately extracts the on-chip power distribution network. It combines speed, capacity, and accuracy for the RLC extraction of the on-chip P/G network. For I/O SSO application, RedHawk limits extraction to the region of interest and outputs the SPICE netlist of the I/O buffers, the P/ G network connecting these buffers, and the decoupling capacitors supporting the I/O ring.

The NSPICE-PI simulator offers true SPICE accuracy with full support of complex transistor level circuits. It uses BLSN technology, a high performance, large capacity solver for transient simulation of Big Linear RLC network and Small Non-linear transistors and directly supports S-parameters for a mixed-domain simulation.

NSPICE-PI provides concurrent simulation of the Vdd/Vss network, I/O buffer transistor netlist, and distributed RLC, S-parameter, or W-parameter package/PCB models. NSPICE-PI can simulate the power/ground peak noise, crosstalk between signals, and the impact of the power/ground noise on the signal. It also simulates the impact of a spike on the signal created by the output driver or detected by the input receiver.

NSPICE-PI is not dependent on creating a simplified model for any part of the design. Therefore, simulation results are more accurate when determining the ground bounce, impact on output timing (jittering), and signal integrity. The capacity of NSPICE-PI has been proven on netlists of above 300 I/O cells and 100+ port S-parameters. Vdd and Vss mesh networks of larger than 1M nodes and 5M RLCs have been simulated successfully.

Resources:

Global I/O SSO Analysis - EPEP 2004

Article: Power Integrity Requires Global I/O SSO Analysis

Whitepaper