Dynamic Voltage Drop and Impact to Timing
As designs transition to 130nm and 90nm process technologies, full-chip dynamic power integrity becomes a major design challenge and Dynamic Voltage Drop (DvD) and it's impact on chip timing and yield, a major concern. Dynamic power issues are growing cause of silicon re-spins, especially as supply voltages drop and operating frequency increases.

Existing static IR-drop signoff flow is based on "average" chip toggling rates on a resistance power grid and does not consider the effects of simultaneous switching outputs (core, memory, I/O) decoupling capacitance (intentional and intrinsic), package RLC, and on-chip inductive Ldi/dt on supply voltages.

Other method such as pseudo dynamic analysis, where clock cycle is divided into many windows and performs sequential static analysis on each window is not adequate or sufficiently accurate. A transient analysis is the only way to accurately understand the effects of capacitance and inductance on the power grid and how the dynamic supply noise impacts the timing of the design. If the transient voltage drop is significant, and happens during an important switching window, then the timing of the cells can be affected and can potentially cause the device to fail or run at a slower speed.

RedHawk's full-chip DvD analyses produces outputs for timing analysis tools, comprised of voltage waveform for Vdd and Vss of each cell in the design for a realistic worst-case clock cycle. Apache uses its own proprietary power library (APL) tool to accurately characterize the dynamic power for each cell based on its current waveforms. A methodology that integrates the dynamic analysis capabilities of RedHawk with static timing analysis (STA) tools delivers the most accurate results for evaluating the impact of DvD on timing.

RedHawk supports the following levels of timing analysis.

Instance-level

• Provides instance-based DvD impact on delay and slack.

Path-level

• Provides DvD impact on critical paths reported by STA tools.

Chip-level

• Provides effective Vdd for each cell over its switching timing window, which can be read by STA tools to accurately predict delay and timing.
• Provides Modified SDF (MSDF) based on DvD analysis, which can be read by industry's leading STA tools to achieve timing closure and sign-off.

DvD can have significant impact to the statically verified timing of a design. Designs that pass "golden" static sign-off may fail due to timing issues caused by dynamic supply noise. RedHawk's full-chip dynamic physical power analysis capability enables timing analysis tools to predict delay and timing more accurately and reach timing closure more reliably.