Timing sign-off for critical path and clock network
in nanometer designs.

As designs move towards 90 nanometer processes and below, timing sign-off based on static timing analysis (STA) alone is no longer adequate.  For nanometer designs, the concurrent effects of power and signal integrity must be considered to understand the realistic silicon behavior.  In addition, the analysis must be performed using Spice – the “ultimate truth” in circuit simulation to see the real timing impact of SoC noise.

For critical path analysis, the setup and hold time margin can dramatically differ when dynamic voltage drop and ground bounce effects are included for each instance in the path. By compounding this effect with signal transition coupling from a neighboring net, a critical path that showed a positive slack in a standard STA report could in fact have negative slack, resulting in timing failures. Likewise, the effects of power and signal integrity can significantly impact the skew and cause delay and jittering in a clock network.

Impact of PI and SI noise on timing

PsiWinder from Apache Design Solutions delivers standard-cell ease-of-use and capacity with a Spice-accurate simulation of critical timing paths and clock tree network. PsiWinder includes all the nanometer and high-speed effects such as crosstalk and DvD in its analysis.

PsiWinder is tightly integrated with Apache’s RedHawk, a SoC dynamic power integrity solution, providing sign-off quality input for the analysis of DvD effects. PsiWinder also utilizes Apache’s NSPICE, a true-Spice simulator, which uses proprietary BLSN (big linear, small non-linear) technology to accelerate the simulation of networks that have an enormous number of linear elements, and a smaller number of non-linear elements. While PsiWinder uses NSPICE “under the hood”, it provides the ease of use of a cell-based flow for the designers by automatically generating the SPICE netlist and vectors, and reading in and producing out standard STA report format.

For designs using 90 nanometer and below processes, verifying the critical path and clock network timing based on Spice-accurate simulation, with the effects of concurrent power and signal integrity will become a critical step in timing sign-off.