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Mission
Apache Design Solutions’ mission is to deliver advanced physical design and verification technology and tools that enable nanometer Systems-on-a-Chip (SOC) markets to accelerate chip design and guarantee silicon for power, timing, and signal integrity. Apache’s physical power integrity products are targeted for massive digital/analog SOCs operating at ultra-high frequencies.
About Apache
Apache Design Solutions was founded in March 2001 by Andrew Yang, Shen Lin, Norman Chang, and a development team of Ph.D.E.E. physical design specialists with more than 80 years of combined expertise in EDA and semiconductor chip design.
Apache delivers innovative next-generation physical power integrity software for power, timing, and system I/O integrity that accelerates the design process and guarantees the reliability of high performance SOCs. Apache’s products are used early and throughout the design process, delivering the highest standards of computational performance, capacity handling, and integrity.
Market
Power integrity has become a required "sign-off" criteria as designs move past 130nm and into 90nm, 65nm, and below. Without accurate power analysis, chips are likely to experience logic and timing failures due to dynamic power supply noise from simultaneous switching of logic, memory, and I/Os. Apache’s products fill the missing link in existing “static-only” physical design flow used by major semiconductor manufactures in various market segments such as networking, wireless, communications, computer, and consumer. Apache delivers the only silicon proven, full-chip vectorless dynamic power integrity solution with transistor-level accuracy for high performance SOCs.
Products
RedHawk
RedHawk is a full-chip Vectorless Dynamic™ physical power integrity solution delivering cell-based speed and capacity with SPICE-level accuracy. It identifies transient power/ground “hot-spots” from simultaneous switching of core, memory, and I/O, including the effects of on/off-chip inductance and intentional/intrinsic decoupling capacitance - effects ignored by static-IR sign-off. RedHawk also addresses verification issues associated with low-power techniques, such as leakage current, power gating, multiple voltages and multiple thresholds.
RedHawk enables designers to examine the power and timing impacts on a SOC caused by the physical implementation decisions made from early design stage through final verification and fills the critical missing link for physical power flows in 130nm, 90nm and 65nm SoC designs.
NSPICE
NSPICE is a high capacity, mixed-domain next-generation SPICE for I/O, signal, and power integrity of chips and multi-gigabit systems. For high speed I/Os and interfaces to multi-port/multi-gigabit systems, NSPICE directly takes in S-parameter data and accurately simulates a combination of IC-package-board-connector-backplane topologies. NSPICE is fully HSPICE compatible, with unprecedented performance and capacity while delivering true-SPICE accuracy.
For I/O SSO, NSPICE-PI enables for the first time, true-SPICE simulation of hundreds of I/O buffers together with the extracted power-ground network. NSPICE-PI adds BLSN (Big Linear, Small Non-linear) solver, on top of the C++ modern data structure NSPICE engine.
PsiWinder
PsiWinder is a Spice-based critical path and clock network timing sign-off solution for high-performance nanometer designs. It considers the concurrent effects of power and signal integrity on chip's timing. PsiWinder provides true-Spice accuracy while delivering cell-based ease-of-use and performance. With PsiWinder, designers gain visibility to true silicon behavior, allowing them to focus on the real timing issues.
Contacts
Press Contact:
Cayenne Communication - Michelle Clancy
(252) 940-0981
michelle.clancy@cayennecom.com
Company Contact:
Yukari Chin
(650) 641-4200
yukari@apache-da.com
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